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King Billion Electronics Co., Ltd

HE84760
HE80000 SERIES
- Table of Contents 1. 2. 3. 4. 5. 6. 7. 7.1. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. General Description ___________________________________________________________________2 Features _____________________________________________________________________________2 Functional Block Diagram ______________________________________________________________3 Pin Description _______________________________________________________________________4 Pad Location _________________________________________________________________________7 LCD RAM Map _____________________________________________________________________10 LCD Power Supply ___________________________________________________________________11 LCDC Control register _____________________________________________________________14 Oscillators __________________________________________________________________________14 General Purpose I/O__________________________________________________________________16 Key Scan Circuit___________________________________________________________________18 Timer1 ___________________________________________________________________________19 Timer2 ___________________________________________________________________________20 Time Base Interrupt________________________________________________________________22 Watch Dog Timer __________________________________________________________________22 Digital-to-Analog Converter _________________________________________________________23 Pulse-Width Modulation ____________________________________________________________24 Dual-Tone Multiple Frequency Generator______________________________________________25 Absolute Maximum Rating __________________________________________________________27 Recommended Operating Conditions _________________________________________________27 AC/DC Characteristics _____________________________________________________________28 Application Circuit_________________________________________________________________29 Important Note ____________________________________________________________________30 Updated Record ___________________________________________________________________31
August 15, 2003
Page 1 of 31
V1.2
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd

HE84760
HE80000 SERIES
1. General Description
HE84760 is a member of 8-bit Micro-controller series developed by King Billion Electronics. There are 3 LCD configurations: 32COM x 96SEG, 48 COM x 80 SEG and 64 COM x 64 SEG available by mask option. 24 LCD segment driver pins are multiplexed with I/O pins to provide flexibility of wide variety of combinations to suit the needs of applications. The built-in LCD power supply is equipped with voltage charge pump to generate the high voltage required by the high duty LCD driver, bias voltage generating circuit and input voltage regulator circuit to supply stable LCD display effect over the wide battery life. The built-in OP comparator can be used with (light, voice, temperature, humility) sensor or battery low detection. Built-in two-channel sinusoidal wave generator can be used to generate telecom tones such as DTMF tone dialing signal, Caller Alerting Signal (CAS) tone, FSK signal as well other tones with frequencies ranging from 1 ~ 4095 Hz. A 7-bit current type D/A converter and PWM device provide the complete speech output mechanism. The 512K byte ROM and 4K byte RAM can be used as the storage of large speech data, graphic, text, etc. It is ideal for applications such as Translator, Data Bank, Educational Toy, Digital Voice Recording System, Short Message Service phone, etc. The instruction set of HE80000 series is easy to learn and simple to use. Only 32 instructions with four addressing modes are provided. Most of instructions take only 3 oscillator clocks to execute. The performance and low power consumption make it suitable for battery-powered applications such as translator, data bank, educational toy, digital voice recorder, etc.
2. Features
Operation Voltage: Internal ROM: Internal RAM: Dual Clock System: 2.4V ~ 3.6V 512 KB (256K Program ROM+256K Data ROM) 4 KB Fast clock: 32768 ~ 8M Hz Slow clock: 32768 Hz 4 operation modes: Fast, Slow, Idle, and Sleep modes. 16 ~ 40 bit bi-directional general purpose I/O ports with push-pull or open-drain output type selectable for each I/O pin by mask option. Built-in 4x20 hardware keyboard scan circuit (multiplexed with LCD SEG pin) helps to reduce the pin counts as well as the firmware effort. Three LCD configurations: 32COM x 96SEG, 48 COM x 80 SEG and 64 COM x 64 SEG. Built-in LCD power supply with input voltage regulator, voltage charge pump and bias voltage generating circuit. LCD Segment Extender Interface to connect with KDS80. One 7-bit current type D/A with mask option to select different output current to prevent signal saturation. Built-in RC oscillator, accuracy at 5%, maximum frequency up to around 10 MHz Single-ended Pulse Width Modulation output for alternate voice output. Built-in OP comparator. Built-in Power on Reset circuit. Two external interrupts and three internal timer interrupts. August 15, 2003 Page 2 of 31 V1.2
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Two 16-bit timers and one Time-Base timer. Watch Dog Timer to prevent deadlock condition. Instruction set: 32 instructions with 4 addressing modes.
HE84760
HE80000 SERIES
3. Functional Block Diagram
SEG COM
LCD Driver LCD Extender Interface LCD Power Supply I/O Port
8 Bit CPU 512 KB ROM 4 KB RAM
Fast Clock OSC. Slow Clock OSC PWM
FXI, FXO
LFR, LDL
SXI, SXO
LVL[1..5], LCDGS,
PWM
TC1 TC2 TBI
PRTC, PRTD, PRT10, PRT17
DAC
VO, DAO
SGKY[43..24]
Key Scan
WDT
OP Amp
OPO,OPIN, OPIP
August 15, 2003
Page 3 of 31
V1.2
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King Billion Electronics Co., Ltd

HE84760
HE80000 SERIES
4. Pin Description
104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 PWM GND_PWM PRTD0 PRTD1 PRTD2 PRTD3 PRTD4 PRTD5 PRTD6 PRTD7 103 102 101 100 99 98 97 96 95 94 PRTC7 PRTC6 PRTC5 PRTC4 VDD_RAM CMSG32 CMSG33 CMSG34 CMSG35 CMSG36 CMSG37 CMSG38 CMSG39 CMSG40 CMSG41 CMSG42 CMSG43 CMSG44 CMSG45 CMSG46 CMSG47 CMSG48 CMSG49 CMSG50 CMSG51 CMSG52 CMSG53 CMSG54 CMSG55 CMSG56 CMSG57 CMSG58 CMSG59 CMSG60 CMSG61 CMSG62 CMSG63 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SGKY 43 SGKY 42 SGKY 41 SGKY 40 SGKY 39 SGKY 38 SGKY 37 SGKY 36 SGKY 35 SGKY 34 SGKY 33 SGKY 32 SGKY 31 SGKY 30 SGKY 29 SGKY 28 SGKY 27 SGKY 26 SGKY 25 SGKY 24 PRT147 PRT146 PRT145 PRT100 PRT101 PRT102 PRT103 TRIM0 TGND1 TRIM1 TRIM2 TGND2 TRIM3 VDD SXI SXO TSTP_P FXI FXO RSTP_N OPO OPIP OPIN VO GND LDL LFR LCAP2A LCAP3B LCAP2B LCAP1B LCAP1A LVL2 LVL1 LCDVX LCAP3A LCAP4A LCAP4B LCDVTB LVL3 LVL4 LVL5 LCDGS COM0 COM1 COM2 C0M3 C0M4 C0M5 C0M6 C0M7 C0M8 C0M9 C0M10 C0M11 C0M12 C0M13 C0M14 C0M15 C0M16 C0M17 C0M18 C0M19 C0M20 C0M21 C0M22 C0M23 C0M24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 PRT170 PRT171 PRT172 PRT173 PRT174 PRT175 PRT176 PRT177 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
HE84760
August 15, 2003
1 2 3 4 5 6 7 8 9 10 11 12 13
PRT144 PRT143 PRT142 PRT141 PRT140 PRT157 PRT156 PRT155 PRT154 PRT153 PRT152 PRT151 PRT150
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V1.2
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King Billion Electronics Co., Ltd
Pin Name Pin # I/O 181~ 183, 1~5
HE84760
HE80000 SERIES

PRT14[7..0]
B/ O
PRT15[7..0]
6 ~ 13
B/ O
PRT17[7..0]
14 ~ 21
B/ O
COM[31..0] LCDGS LVL5 LVL4 LVL3 LCDVTB LCAP4B LCAP4A LCAP3A LCDVX LVL1 LVL2 LCAP1A LCAP1B LCAP2B LCAP3B LCAP2A LFR LDL GND VO OPIN OPIP OPO RSTP_N FXO, FXI
22~53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78, 79
O B B B B B B B B B B B B B B B B O O P O I I O I O, B
Description 8-bit bi-directional I/O port 14 is shared with LCD segment pads SEG[23..16]. The function of the pad can be selected individually by mask options MO_LIO14[7..0]. (`1' for LCD and `0' for I/O). The output type of I/O pad can also be selected by mask option MO_14PP[7..0] (1 for push-pull and `0' for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, "1" must be outputted before reading. 8-bit bi-directional I/O port 15 is shared with LCD segment pads SEG[16..8]. The function of the pad can be selected individually by mask options MO_LIO15[7..0]. (`1' for LCD and `0' for I/O). The output type of I/O pad can also be selected by mask option MO_15PP[7..0] (1 for push-pull and `0' for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, "1" must be outputted before reading. 8-bit bi-directional I/O port 17 is shared with LCD segment pads SEG[7..0]. The function of the pad can be selected individually by mask options MO_LIO17[7..0]. (`1' for LCD and `0' for I/O). The output type of I/O pad can also be selected by mask option MO_17PP[7..0] (1 for push-pull and `0' for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, "1" must be outputted before reading. LCD COMMON Driver pads. LCD Voltage setting. Adjust Resistor between LCDGS and LVL2 to set LVL5. LCD Bias Voltage 5 LCD Bias Voltage 4 LCD Bias Voltage 3 Charge Pump Capacitor Pin Charge Pump Capacitor Pin. Charge Pump Capacitor Pin Charge Pump Capacitor Pin Charge Pump Capacitor Pin LCD Bias Voltage 1 LCD Bias Voltage 2 Charge Pump Capacitor Pin Charge Pump Capacitor Pin Charge Pump Capacitor Pin Charge Pump Capacitor Pin Charge Pump Capacitor Pin LCD frame signal for interfacing with LCD segment extender KDS80. LCD data load pin for interfacing with LCD segment extender KDS80. Power ground Input. DAC Output. Inverting input of OP Amp. Set the bit 0 (OP = 1) of VOC register to turn on OP comparator. Non-inverting input of OP Amp. Output of OP Amp. System Reset input pin. Level trigger, active low on this pin will put the chip in reset state. External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (`0' for RC type and `1' for crystal type). For RC type oscillator, one resistor needs to be connected between FXI and GND. For crystal oscillator, one crystal needs to be placed between FXI and FXO. Please refer to application circuit for details.
August 15, 2003
Page 5 of 31
V1.2
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King Billion Electronics Co., Ltd
Pin Name TSTP_P SXO, SXI VDD TGND2 TGND1 Pin # I/O 80 81, 82 83 85 88 I O, I P P P
HE84760
HE80000 SERIES

PRT10[3:0]
90~93
B
PRTD[7..0]
94~101 B
GND_PWM PWM
102 103
O O
PRTC[7:4]
104~107 B
VDD_RAM
108
P
CMSG[32..63] 109~140 O SEG[63..44] 141~160 O SGKY[43..24] 161~180 O
Description Test input pin. Please bond this pad and reserve a test point on PCB for debugging. But for improving ESD, please connect this point with zero Ohm resistor to GND. External slow clock pins. Slow clock is clock source for LCD display, TIMER1, Time-Base and other internal blocks. Both crystal and RC oscillator are provided. The slow clock type can be selected by mask option MO_SXTAL. Choose `0' for RC type and `1' for crystal oscillator. Positive power Input. 0.1 F decoupling capacitors should be placed as close to IC VDD and GND pads as possible for best decoupling effect. Power Ground Input. The TGND2 should connect with GND pin. Power Ground Input. The TGND1 should connect with GND pin. 4-bit bi-directional I/O port 10. The output type of I/O pad can also be selected by mask option MO_10PP[3..0] (`1' for push-pull and `0' for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O pad as input pad, "1" must be outputted before reading. PRT10[0] is shared with DTMFO of DTMF generator. PRT10[1] is multiplexed with KEYTONE output. 8-bit bi-directional I/O port D. The output type of I/O pad can also be selected by mask option MO_DPP[7..0] (`1' for push-pull and `0' for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, `1' must be outputted before reading the pin. PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be as external interrupt sources. Dedicated Ground for PWM output. The PWM output can drive speaker or buzzer directly. Set the bit2 of VOC register as one to turn on PWM. Using VDD & PWM to drive output device. 8-bit bi-directional I/O port C. The output type of I/O pad can also be selected by mask option MO_CPP[7..0] (`1' for push-pull and `0' for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, `1' must be outputted before reading the pin. PRTC[7:4] is shared with Key Scan Dedicated Input SCNI[3:0]. The Key Scan function can be disabled by clearing MO_LCDKEY mask option to `0'. Dedicated power input for RAM COM[32..63] pads are shared with SEG[95..64] outputs. The functions of the pads to be COM drivers or SEG drivers can be selected by mask option MO_COM[1..0]. Please refer to LCD driver configuration for details. LCD segment SEG[63..44] outputs. LCD segments share pads with key scan out SCNO[19..0]. The key scan function of these pins can be disabled by mask option clearing MO_LCDKEY to `0', then SGKY[43..24] function as LCD segment driver only. Setting MO_LCDKEY to `1' will turn on the key scan function.
I: Input, O: Output, B: Bidirectional, P: Power.
August 15, 2003
Page 6 of 31
V1.2
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King Billion Electronics Co., Ltd
Product Name
HE84760
HE80000 SERIES
5. Pad Location
PRT17[7]/SEG[7] PRT17[6]/SEG[6] PRT17[5]/SEG[5] PRT17[4]/SEG[4] PRT17[3]/SEG[3] PRT17[2]/SEG[2] PRT17[1]/SEG[1] PRT17[0]/SEG[0] COM[31] COM[30] COM[29] COM[28] COM[27] COM[26] COM[25] COM[24] COM[23] COM[22] COM[21] COM[20] COM[19] COM[18] COM[17] COM[16] COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9] COM[8] COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] COM[0] LCDGS LVL5 LVL4 LVL3 LCDVTB LCAP4B LCAP4A LCAP3A LCDVX LVL1 LVL2 LCAP1A LCAP1B LCAP2B LCAP3B LCAP2A LFR LDL GND VO OPIN OPIP OPO RSTP_N FXO FXI TSTP_P SXO SXI VDD NC TGND2 NC NC TGND1 NC PRT10[3] PRT10[2] PRT10[1] PRT10[0 PPPPPPPPPPPPP RRRRRRRRRRRRR TTTTTTTTTTTTT 15 15 15 15 15 15 15 15 14 14 14 14 14 [0] [1] [2] [3] [4] [5] [6] [7] [0] [1] [2] [3] [4] /S /S /S /S /S /S /S /S /S /S /S /S /S EEEEEEEEEEEEE GGGGGGGGGGGGG [[[[[[[[[[[[[ 8 9 10 11 12 13 14 15 16 17 18 19 20 ]]]]]]]]]]]]] PRT14[5] /SEG[21] PRT14[6] /SEG[22] PRT14[7] /SEG[23] SGKY[24] /SCNO[0] SGKY[25] /SCNO[1] SGKY[26] /SCNO[2] SGKY[27] /SCNO[3] SGKY[28] /SCNO[4] SGKY[29] /SCNO[5] SGKY[30] /SCNO[6] SGKY[31] /SCNO[7] SGKY[32] /SCNO[8] SGKY[33] /SCNO[9] SGKY[34] /SCNO[10] SGKY[35] /SCNO[11] SGKY[36] /SCNO[12] SGKY[37] /SCNO[13] SGKY[38] /SCNO[14] SGKY[39] /SCNO[15] SGKY[40] /SCNO[16] SGKY[41] /SCNO[17] SGKY[42] /SCNO[18] SGKY[43] /SCNO[19] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] CMSG[63] CMSG[62] CMSG[61] CMSG[60] CMSG[59] CMSG[58] CMSG[57] CMSG[56] CMSG[55] CMSG[54] CMSG[53] CMSG[52] CMSG[51] CMSG[50] CMSG[49] CMSG[48] CMSG[47] CMSG[46] CMSG[45] CMSG[44] CMSG[43] CMSG[42] CMSG[41] CMSG[40] CMSG[39] CMSG[38] CMSG[37] CMSG[36] CMSG[35] CMSG[34] CMSG[33] CMSG[32] VDD_RAM PRTC[4] PRTC[5] PRTC[6] PRTC[7]
Die Size: 10060 m * 2090 m Substrate connect with GND
G N P P P P P P P PD RRRRRRRR_ T T T T T T T TPP D D D D D D D D WW [7] [6] [5] [4] [3] [2] [1] [0] M M
August 15, 2003
Page 7 of 31
V1.2
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King Billion Electronics Co., Ltd

HE84760
HE80000 SERIES Y Coordinate Y= -970.45 Y= -568.35 Y= -453.35 Y= -338.35 Y= -223.35 Y= -108.35 Y= 6.65 Y= 121.65 Y= 236.65 Y= 351.65 Y= 466.66 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 Y= 969.25 V1.2
PIN Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
PIN Name PRT14[4] PRT14[3] PRT14[2] PRT14[1] PRT14[0] PRT15[7] PRT15[6] PRT15[5] PRT15[4] PRT15[3] PRT15[2] PRT15[1] PRT15[0] PRT17[7] PRT17[6] PRT17[5] PRT17[4] PRT17[3] PRT17[2] PRT17[1] PRT17[0] COM[31] COM[30] COM[29] COM[28] COM[27] COM[26] COM[25] COM[24] COM[23] COM[22] COM[21] COM[20] COM[19] COM[18] COM[17] COM[16] COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9] COM[8]
X Coordinate X= -5005.80 X= -5005.80 X= -5005.80 X= -5005.80 X= -5005.80 X= -5005.80 X= -5005.80 X= -5005.80 X= -5005.80 X= -5005.80 X= -5005.80 X= -5005.80 X= -5005.80 X= -4635.10 X= -4520.10 X= -4405.10 X= -4290.10 X= -4175.10 X= -4060.10 X= -3945.10 X= -3830.10 X= -3715.10 X= -3600.10 X= -3485.10 X= -3370.10 X= -3255.10 X= -3140.10 X= -3025.10 X= -2910.10 X= -2695.10 X= -2580.10 X= -2465.10 X= -2350.10 X= -2235.10 X= -2120.10 X= -2005.10 X= -1890.10 X= -1775.10 X= -1660.10 X= -1545.10 X= -1430.10 X= -1315.10 X= -1200.10 X= -1085.10 X= -970.10
Y PIN PIN Coordinate Number Name Y= 667.00 93 PRT10[0] Y= 552.00 94 PRTD[7] Y= 437.00 95 PRTD[6] Y= 322.00 96 PRTD[5] Y= 207.00 97 PRTD[4] Y= 92.00 98 PRTD[3] Y= -23.00 99 PRTD[2] Y= -138.00 100 PRTD[1] Y= -253.00 101 PRTD[0] Y= -368.00 102 GND_PWM Y= -483.00 103 PWM Y= -598.00 104 PRTC[7] Y= -713.00 105 PRTC[6] Y= -970.45 106 PRTC[5] Y= -970.45 107 PRTC[4] Y= -970.45 108 VDD_RAM Y= -970.45 109 CMSG[32] Y= -970.45 110 CMSG[33] Y= -970.45 111 CMSG[34] Y= -970.45 112 CMSG[35] Y= -970.45 113 CMSG[36] Y= -970.45 114 CMSG[37] Y= -970.45 115 CMSG[38] Y= -970.45 116 CMSG[39] Y= -970.45 117 CMSG[40] Y= -970.45 118 CMSG[41] Y= -970.45 119 CMSG[42] Y= -970.45 120 CMSG[43] Y= -970.45 121 CMSG[44] Y= -970.45 122 CMSG[45] Y= -970.45 123 CMSG[46] Y= -970.45 124 CMSG[47] Y= -970.45 125 CMSG[48] Y= -970.45 126 CMSG[49] Y= -970.45 127 CMSG[50] Y= -970.45 128 CMSG[51] Y= -970.45 129 CMSG[52] Y= -970.45 130 CMSG[53] Y= -970.45 131 CMSG[54] Y= -970.45 132 CMSG[55] Y= -970.45 133 CMSG[56] Y= -970.45 134 CMSG[57] Y= -970.45 135 CMSG[58] Y= -970.45 136 CMSG[59] Y= -970.45 137 CMSG[60] Page 8 of 31
X Coordinate X= 4799.90 X= 4904.30 X= 4904.30 X= 4904.30 X= 4904.30 X= 4904.30 X= 4904.30 X= 4904.30 X= 4904.30 X= 4904.30 X= 4904.30 X= 4737.30 X= 4622.30 X= 4507.30 X= 4392.30 X= 4177.30 X= 4062.31 X= 3947.30 X= 3832.30 X= 3717.30 X= 3602.30 X= 3487.30 X= 3372.30 X= 3257.30 X= 3142.30 X= 3027.30 X= 2912.30 X= 2797.30 X= 2682.30 X= 2567.30 X= 2452.30 X= 2337.30 X= 2122.30 X= 2007.30 X= 1892.30 X= 1777.30 X= 1662.30 X= 1547.31 X= 1432.30 X= 1317.30 X= 1202.30 X= 1087.30 X= 972.30 X= 857.30 X= 742.30
August 15, 2003
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
PIN Number 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 PIN Name COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] COM[0] LCDGS LVL5 LVL4 LVL3 LCDVTB LCAP4B LCAP4A LCAP3A LCDVX LVL1 LVL2 LCAP1A LCAP1B LCAP2B LCAP3B LCAP2A LFR LDL GND VO OPIN OPIP OPO RSTP_N FXO FXI TSTP_P SXO SXI VDD NC TGND2 NC NC TGND1 NC PRT10[3] PRT10[2] X Coordinate X= -855.10 X= -740.10 X= -625.10 X= -510.10 X= -395.10 X= -280.10 X= -165.10 X= -50.10 X= 165.35 X= 280.35 X= 395.35 X= 510.35 X= 625.35 X= 740.35 X= 855.35 X= 970.35 X= 1085.35 X= 1200.35 X= 1315.35 X= 1430.35 X= 1695.35 X= 1810.35 X= 1925.35 X= 2040.35 X= 2154.90 X= 2269.90 X= 2384.90 X= 2499.90 X= 2614.90 X= 2729.90 X= 2844.90 X= 2959.90 X= 3074.90 X= 3189.90 X= 3304.90 X= 3419.90 X= 3534.90 X= 3649.90 X= 3764.90 X= 3879.90 X= 3994.90 X= 4109.90 X= 4224.90 X= 4339.90 X= 4454.90 X= 4569.90
HE84760
HE80000 SERIES
Y PIN PIN X Y Coordinate Number Name Coordinate Coordinate Y= -970.45 138 CMSG[61] X= 627.30 Y= 969.25 Y= -970.45 139 CMSG[62] X= 512.30 Y= 969.25 Y= -970.45 140 CMSG[63] X= 397.30 Y= 969.25 Y= -970.45 141 SEG[63] X= 282.30 Y= 969.25 Y= -970.45 142 SEG[62] X= 167.30 Y= 969.25 Y= -970.45 143 SEG[61] X= 52.30 Y= 969.25 Y= -970.45 144 SEG[60] X= -62.70 Y= 969.25 Y= -970.45 145 SEG[59] X= -177.70 Y= 969.25 Y= -969.70 146 SEG[58] X= -292.70 Y= 969.25 Y= -969.70 147 SEG[57] X= -407.70 Y= 969.25 Y= -969.70 148 SEG[56] X= -522.70 Y= 969.25 Y= -969.70 149 SEG[55] X= -637.70 Y= 969.25 Y= -969.70 150 SEG[54] X= -852.69 Y= 969.25 Y= -969.70 151 SEG[53] X= -967.69 Y= 969.25 Y= -969.70 152 SEG[52] X= -1082.69 Y= 969.25 Y= -969.70 153 SEG[51] X= -1197.69 Y= 969.25 Y= -969.70 154 SEG[50] X= -1312.69 Y= 969.25 Y= -969.70 155 SEG[49] X= -1427.69 Y= 969.25 Y= -969.70 156 SEG[48] X= -1542.69 Y= 969.25 Y= -969.70 157 SEG[47] X= -1657.69 Y= 969.25 Y= -969.70 158 SEG[46] X= -1772.69 Y= 969.25 Y= -969.70 159 SEG[45] X= -1887.69 Y= 969.25 Y= -969.70 160 SEG[44] X= -2002.69 Y= 969.25 Y= -969.70 161 SGKY[43] X= -2117.69 Y= 969.25 Y= -970.45 162 SGKY[42] X= -2232.69 Y= 969.25 Y= -970.45 163 SGKY[41] X= -2347.69 Y= 969.25 Y= -970.45 164 SGKY[40] X= -2462.69 Y= 969.25 Y= -970.45 165 SGKY[39] X= -2577.69 Y= 969.25 Y= -970.45 166 SGKY[38] X= -2692.69 Y= 969.25 Y= -970.45 167 SGKY[37] X= -2807.69 Y= 969.25 Y= -970.45 168 SGKY[36] X= -2922.69 Y= 969.25 Y= -970.45 169 SGKY[35] X= -3037.69 Y= 969.25 Y= -970.45 170 SGKY[34] X= -3152.69 Y= 969.25 Y= -970.45 171 SGKY[33] X= -3267.69 Y= 969.25 Y= -970.45 172 SGKY[32] X= -3382.69 Y= 969.25 Y= -970.45 173 SGKY[31] X= -3497.69 Y= 969.25 Y= -970.45 174 SGKY[30] X= -3612.69 Y= 969.25 Y= -970.45 175 SGKY[29] X= -3727.69 Y= 969.25 Y= -970.45 176 SGKY[28] X= -3842.69 Y= 969.25 Y= -970.45 177 SGKY[27] X= -3957.69 Y= 969.25 Y= -970.45 178 SGKY[26] X= -4072.69 Y= 969.25 Y= -970.45 179 SGKY[25] X= -4187.69 Y= 969.25 Y= -970.45 180 SGKY[24] X= -4302.69 Y= 969.25 Y= -970.45 181 PRT14[7] X= -4417.69 Y= 969.25 Y= -970.45 182 PRT14[6] X= -4532.69 Y= 969.25 Y= -970.45 183 PRT14[5] X= -4647.69 Y= 969.25 Page 9 of 31 V1.2
August 15, 2003
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PIN PIN X Y PIN Number Name Coordinate Coordinate Number 92 PRT10[1] X= 4684.90 Y= -970.45 PIN Name X Coordinate
HE84760
HE80000 SERIES Y Coordinate
6. LCD RAM Map
There are 3 LCD configurations as determined by mask option MO_COM. The RAM Maps of all four different LCD configurations are as the following: The functions of CMSG[79..32] are different in each configuration as listed in the following table. MO_COM[1:0] Configuration CMSG[63..48] CMSG[47..32] 00 32 x 96 SEG[64..79] SEG[80..96] 01 48 x 80 SEG[64..79] COM[47..32] 10 64 x 64 COM[63..48] COM[47..32] 11 reserved reserved reserved
COMXSEG CMSG32 CMSG33 CMSG34 CMSG35 CMSG36 CMSG37 CMSG38 CMSG39 CMSG40 CMSG41 CMSG42 CMSG43 CMSG44 CMSG45 CMSG46 CMSG47 CMSG48 CMSG49 CMSG50 CMSG51 CMSG52 CMSG53 CMSG54 CMSG55 CMSG56 CMSG57 CMSG58 CMSG59 CMSG60 CMSG61 CMSG62 CMSG63 32X96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 48X80 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 64X64 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63
32 COM Page SEG 7,6 [7:0] COM0 7E0H COM1 7E1H : : COM15 7EFH COM16 7F0H : : COM30 7FEH COM31 7FFH August 15, 2003
SEG [15:8] 7C0H 7C1H : 7CFH 7D0H : 7DEH 7DFH
SEG [23:16] 7A0H 7A1H : 7AFH 7B0H : 7BEH 7BFH
SEG [31:24] 780H 781H : 78FH 790H : 79EH 79FH
SEG [39:32] 760H 761H : 76FH 770H : 77EH 77FH
SEG [47:40] 740H 741H : 74FH 750H : 75EH 75FH
SEG [55:48] 720H 721H : 72FH 730H : 73EH 73FH
SEG [63:56] 700H 701H : 70FH 710H : 71EH 71FH
SEG [71:64] 6E0H 6E1H : 6EFH 6F0H : 6FEH 6FFH
SEG [79:72] 6C0H 6C1H : 6CFH 6D0H : 6DEH 6DFH
SEG SEG [87:80] [95:88] 6A0H 680H 6A1H 681H : : 6AFH 68FH 6B0H 690H : : 6BEH 69EH 6BFH 69FH V1.2
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48 COM Page 7,6 COM0 COM1 : COM15 COM16 : COM31 COM32 : COM46 COM47 64 COM: Page 7 COM0 COM1 : COM15 COM16 : COM31 COM32 : COM47 COM48 : COM62 COM63 SEG [7:0] 7C0H 7C1H : 7CFH 7D0H : 7DFH 7E0H : 7EFH 7F0H : 7FEH 7FFH SEG [15:8] 780H 781H : 78FH 790H : 79FH 7A0H : 7AFH 7B0H : 7BEH 7BFH SEG [23:16] 740H 741H : 74FH 750H : 75FH 760H : 76FH 770H : 77EH 77FH SEG [31:24] 700H 701H : 70FH 710H : 71FH 720H : 72FH 730H : 73EH 73FH Page 6 COM0 COM1 : COM15 COM16 : COM31 COM32 : COM47 COM48 : COM62 COM63 SEG SEG [39:32] [47:40] 6C0H 680H 6C1H 681H : : 6CFH 68FH 6D0H 690H : : 6DFH 69FH 6E0H 6A0H : : 6EFH 6AFH 6F0H 6B0H : : 6FEH 6BEH 6FFH 6BFH
HE84760
HE80000 SERIES SEG [79:72] 580H 581H : 58FH 590H : 59FH 5A0H : 5AEH 5AFH
SEG SEG SEG SEG SEG SEG SEG SEG SEG [7:0] [15:8] [23:16] [31:24] [39:32] [47:40] [55:48] [63:56] [71:64] 7C0H 780H 740H 700H 6C0H 680H 640H 600H 5C0H 7C1H 781H 741H 701H 6C1H 681H 641h 601H 5C1H : : : : : : : : : 7CFH 78FH 74FH 70FH 6CFH 68FH 64FH 60FH 5CFH 7D0H 790H 750H 710H 6D0H 690H 650H 610H 5D0H : : : : : : : : : 7DFH 79FH 75FH 71FH 6DFH 69FH 65FH 61FH 5DFH 7E0H 7A0H 760H 720H 6E0H 6A0H 660H 620H 5E0H : : : : : : : : : 7EEH 7AEH 76EH 72EH 6EEH 6AEH 66EH 62EH 5EEH 7EFH 7AFH 76FH 72FH 6EFH 6AFH 66FH 62FH 5EFH
SEG [55:48] 640H 641H : 64FH 650H : 65FH 660H : 66FH 670H : 67EH 67FH
SEG [63:56] 600H 601H : 60FH 610H : 61FH 620H : 62FH 630H : 63EH 63FH
7. LCD Power Supply
The built-in LCD power supply is equipped with input voltage regulator, voltage charge pump and bias voltage generating circuit with active buffer instead of passive resistor voltage dividing network. The input voltage is regulated to LVL2 using the internally generated reference voltage. LVL2 can be adjusted by resistor between LCDGS and LVL2. LVL2 adjustment guideline: First, the level of VDD must be 0.3 volt higher than LVL2 even at the end of battery life for the regulator to function properly. For example, if the VDD is expected to drop to 2.2 volts when battery is low, then the level of LVL2 can only be set at 1.9 volts max. The August 15, 2003 Page 11 of 31 V1.2
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Voltage charge pump: The LVL2 is then pumped to LVL5 based on the bias setting of MO_LBSR[3..0]. The formula for LVL5 is: LVL5 = LVL2 / 2 x (1/Bias) The potential difference between bias voltages LVL1 ~ LVL5 is determined by the bias settings, too.
Voltage Difference Ratio LVL5 1 1 3 ~ 6.5 1 1 LVL4 LVL3 LVL2 LVL1
For example, if the bias setting is 1/7 bias and LVL2 is 2 volts, the LVL5 will be pumped to 7 volts when the load is light. Bias Min. VDD LVL2 2.70 2.40 2.60 2.30 2.50 2.20 2.40 2.10 2.30 2.00 2.20 1.90 2.10 1.80 2.00 1.70 5.0 6.00 5.75 5.50 5.25 5.00 4.75 4.50 4.25 5.5 6.60 6.33 6.05 5.78 5.50 5.23 4.95 4.68 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 LVL5 = LCD Panel Operating Voltage 7.20 7.80 8.40 6.90 7.48 8.05 6.60 7.15 7.70 8.25 6.30 6.83 7.35 7.88 8.40 6.00 6.50 7.00 7.50 8.00 8.50 5.70 6.18 6.65 7.13 7.60 8.08 8.55 5.40 5.85 6.30 6.75 7.20 7.65 8.10 8.55 5.10 5.53 5.95 6.38 6.80 7.23 7.65 8.08 8.5 6.0
Please note that external connections of charge pump capacitors must be made according to the bias setting, too. Please use the following figure as reference when designing application circuit and LVL5 must be lower than 8.5 volts to prevent chip from breaking down.
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For bias: 5, 5.5, 6 1uF 1uF 1uF LVL5 LVL4 LVL3 LCAPVTB LCAP4B 1uF LCAP4A LCAP3B 1uF LCAP3A LCAP2B LCAP2A LCAP1B LCAP1A LCDGS 1uF 1uF 1uF R LVL2 LVL1 LCDVX 1uF 1uF 1uF R 1uF 1uF 1uF
HE84760
HE80000 SERIES
LVL5 LVL4 LVL3 LCAPVTB LCAP4B

For bias: 6.5, 7, 7.5, 8 1uF 1uF 1uF LVL5 LVL4 LVL3 LCAPVTB LCAP4B LCAP4A LCAP3B LCAP3A LCAP2B LCAP2A LCAP1B LCAP1A LCDGS LVL2 LVL1 LCDVX
For bias: 8.5, 9, 9.5, 10 1uF 1uF 1uF
1uF
LCAP4A LCAP3B
1uF
LCAP3A LCAP2B
1uF
LCAP2A LCAP1B
1uF
LCAP1A LCDGS
1uF 1uF 1uF
R
LVL2 LVL1 LCDVX
Different duties require different bias settings. There is some reference correspondence between the Duty and Bias Setting. However, it is better to use it as starting point and adjust it with real LCD panel connected to it to determine the final setting. The relationship between the duty and bias setting is just for reference as following: Duty Cycle Normal Bias Alternative Bias 32 duty 1/7 1/7.5 48 duty 1/8 1/7.5, 1/8.5 64 duty 1/9 1/8.5, 1/9.5 The bias setting is made by mask option MO_LBSR[3..0]. MO_LBSR[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 August 15, 2003 Bias Setting undefined 1/5 1/5.5 1/6 1/6.5 1/7 1/7.5 1/8 1/8.5 1/9 1/9.5 1/10 1/10.5 1/11 1/11.5 V1.2
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1111 1/12
HE84760
HE80000 SERIES
7.1. LCDC Control register
The gray scale of the LCD driver can be adjusted by GRAY field of LCD. The LCD panel can be blanked by setting the BLANK field of LCDC register. LCD driver can be totally turned off by clearing LCDE bit of LCDC. LCDC Field Reset Field GRAY bit 7 bit 6 bit 5 bit 4 bit 3 GRAY bit 2 bit 1 BLANK 1 bit 0 LCDE 0
Value 000 111 BLANK 0 1 LCDE 0 1
Function LCD is darkest. LCD is lightest. normal display LCD display blanked. The COM signals of LCD driver output inactive levels (LVL4 and LVL1) while SEG signals output normal display patterns. LCD driver disabled, LCD driver has no output signal. LCD driver Enabled
Please note that LCD driver must be turned off before the MCU goes into sleep mode. In other words, user must clear the bit 0 (LCDE bit) of LCDC to turn off LCD driving circuit before setting bit6 of OP1 to enter sleep mode. Large current might happen if the procedure is not followed. Please note that LCD driver uses slow clock as clock source. The LCD display would not display normally if it worked in Fast clock only mode as the LCD refresh action would be too fast.
8. Oscillators
The MCU is equipped with two clock sources with a variety of selections on the types of oscillators to choose from. So that system designer can select oscillator types based on the cost target, timing accuracy requirements etc. Crystal, Resonator or the RC oscillator can be used as fast clock source, components should be placed as close to the pins as possible. The type of oscillator used is selected by mask option MO_FXTAL. MO_FXTAL 0 1 Fast clock type RC Oscillator. Crystal Oscillator.
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FXI FXI 22p R 3579545Hz 22p FXO Crystal Osc. RC Osc.
HE84760
HE80000 SERIES

The RC oscillator has a built-in capacitor. An external resistor is needed to connect from FXI to GND to determine the oscillation frequency. The capacitance of internal RC oscillator is selected by mask option MO_RCAP[2..0]. MO_RCAP[2..0] Internal RC Cap. OSC. (pF) 000 2 001 4 010 7 011 14 100 20 101 40 110 50 111 60 The following table shows the combinations of R and C, and the resulting frequency. Please note that oscillation frequency in the table only represents oscillation frequencies of certain samples. The actual oscillation frequency may vary up to 15% from lot to lot due to process parameter variations. User must take this into consideration when using this chip in applications. Ring Oscillator Frequency Table R(K ohm )\C (pF) 30.20 19.92 9.98 40 0.8 1.2 2.3 20 1.5 2.2 4.0 14 2.0 2.8 5.1 7 3.0 4.4 7.5 4 4.0 5.6 9.4 2 5.0 MHz 7.0 MHz 11.4 MHz
Two types of oscillator, crystal and RC, can be used as slow clock by mask option MO_SXTAL. If used for time keeping function or other applications that required the accurate timing, crystal oscillator is recommended. If the timing accuracy is not important, then RC type oscillator can be used to reduce cost. MO_SXTAL 0 1 Slow Clock Type R/C oscillator Crystal oscillator
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SXI SXI
HE84760
HE80000 SERIES

SXO
Crystal Osc.
SXO
RC Osc.
With two clock sources available, the system can switch among operation modes of Fast, Slow, Idle, and Sleep modes by the setting of OP1 and OP2 registers as shown in tables below to suit the needs of application such as power saving, etc. OP1 Field Mode Reset OP2 Field Mode Reset Bit 7 DRDY R/W 1 Bit 7 IDLE R/W 0 Bit 6 STOP R/W 0 Bit 6 PNWK R Bit 5 SLOW R/W 0 Bit 5 TCWK R Bit 4 INTE R/W 0 Bit 4 TBE R/W 0 Bit 3 T2E R/W 0 Bit 3 W Bit 2 T1E R/W 0 Bit 1 Z R/W Bit 0 C R/W Bit 0 W -
Bit 2 Bit 1 TBS[3..0] W W -
If the dual clock mode is used, the LCD display, Timer1 and Timer Base will derive its clock source from slow clock while the other blocks will operate with the fast clock.
9. General Purpose I/O
There are three dedicated general purpose I/O port, PRTC[4..7], PRTD and PRT10[0..3], while PRT14, PRT15 and PRT17 are multiplexed with LCD segment driver pins. All the I/O Ports are bi-directional and of non- tri-state output structure. The output has weak sourcing (50 A) and stronger sinking (1 mA) capability and each can be configured as push-pull or open-drain output structure individually by mask option. When the I/O port is used as input, the weakly high sourcing can be used as weakly pull-up. Open drain can be used if the pull-up is not required and let the external driver to drive the pin. Please note that a floating pad could cause more power consumption since the noise could interfere with the circuit and cause the input to toggle. A `1' needs to be written to port first before reading the input data from the I/O pin. If the PMOS is used as pull-up, care should be taken to avoid the constant power drain by DC path between pull-up and external circuit. The input port has built-in Schmidt trigger to prevent it from chattering. Hysteresis level of Schmidt trigger is 1/3*VDD. August 15, 2003 Page 16 of 31 V1.2
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VDD
HE84760
HE80000 SERIES
VDD
DOUT
Q LATCH Q' MO_?PP
PAD
DIN SCHMIDT Trigger input
As pads of PRT14, PRT15 and PRT17 are shared with LCD segment driver, the function of the pads is determined by mask options.
LIO17=0 PRT170 PRT171 PRT172 PRT173 PRT174 PRT175 PRT176 PRT177 PRT170 PRT171 PRT172 PRT173 PRT174 PRT175 PRT176 PRT177 LIO15=0 PRT150 PRT151 PRT152 PRT153 PRT154 PRT155 PRT156 PRT157 PRT150 PRT151 PRT152 PRT153 PRT154 PRT155 PRT156 PRT157 LIO14=0 PRT140 PRT141 PRT142 PRT143 PRT144 PRT145 PRT146 PRT147 PRT140 PRT141 PRT142 PRT143 PRT144 PRT145 PRT146 PRT147 LIO17=1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 LIO15=1 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 LIO14=1 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23
Following table is the setting for MO_LIO?[...] and MO_?PP[...] and others related to LCD display setting and pin assignment features. MO_LIO?[...] MO_?PP[...] I/O Port LCD Pin 0 0 Open-drain output -0 1 Push-pull output -1 0 -xx 1 1 -LCD Display --: Function not available. xx: Displayable, but may have abnormal leakage current, do not use. August 15, 2003 Page 17 of 31 V1.2
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HE80000 SERIES
10. Key Scan Circuit
The built-in 4x20 hardware keyboard scan circuit helps to reduce the pin counts where application requires large key matrix and high LCD pixel count as well as the firmware effort. As key-scan pins are shared with LCD segment and PRTC4 ~ PRTC7 pins, it is advisable to put resistors between segment pins and key matrix to avoid shorting the segment pins when two or more keys in the same row are pressed simultaneously. Two key can be detected simultaneously and the first detected key code is stored in KEY0 register and the second in KEY1 register respectively. The key code for each key location is listed in the following table. Key Loc SCNI0 SCNO0 0x80 SCNO1 0x81 SCNO2 0x82 SCNO3 0x83 SCNO4 0x84 SCNO5 0x85 SCNO6 0x86 SCNO7 0x87 SCNO8 0x88 SCNO9 0x89 SCNO10 0x8A SCNO11 0x8B SCNO12 0x8C SCNO13 0x8D SCNO14 0x8E SCNO15 0x8F SCNO16 0x90 SCNO17 0x91 SCNO18 0x92 SCNO19 0x93 SCNI1 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 SCNI2 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 SCNI3 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3
KEY0 0x22 KEY1 0x23
BIT7 R BIT7 R
BIT6 BIT5 Row Index BIT6 BIT5 Row Index
BIT4
BIT3
BIT2 BIT1 Column Index BIT2 BIT1 Column Index
BIT0
BIT4
BIT3
BIT0
The bit 7 of KEY0 and KEY1 is repeat indicator when the same key is scanned for the second time, the R bit will be cleared to indicate the key is not released yet. The key-scan function can be turned on/off by mask option MO_LCDKEY. MO_LCDKEY 0 August 15, 2003 SGKY[43..24] Function as SEG only Page 18 of 31 V1.2
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1 as SEG as well as KEY_SCAN
HE84760
HE80000 SERIES
The pulse width of key-scan signal can be selected by mask options MO_SNCK[1..0]. MO_SNCK[1..0] 00 01 10 11 Key Scan Pulse Width 0.5 sck 1 sck 1.5 sck 2 sck
The strength of key-scan signal can also be selected by mask options MO_SNCK[1..0]. MO_SCDRV[1..0] 00 01 10 11 Key Scan Signal Strength weakest
strongest
SCNO0 SCNO1 SCNO2 SCNO3 SCNO17 SCNO18 SCNO19 SCNI0 SCNI1 SCNI2 SCNI3
SGKY 24 SGKY 25 SGKY 26 SGKY 27 : SGKY 41 SGKY 42 SGKY 43 47K PRTC4 PRTC5 PRTC6 PRTC7
47K 47K 47K ....
47K
47K
47K
11. Timer1
The Timer1 consists of two 8-bit write-only preload registers T1H and T1L and 16-bit down counter. If Timer1 is enabled, the counter will decrement by one with each incoming clock pulse. Timer1 interrupt will be generated when the counter underflows - counts down to FFFFH. And the counter will be automatically reloaded with the value of T1H and T1L. The clock source of Timer1 is derived from slow clock "SCK" at dual clock or slow clock only mode. And it comes from the fast clock "FCK" at fast clock only mode. Please note that the interrupt is generated when counter counts from 0000H to FFFFH. If the value of T1H and T1L is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when system resets. Once it is enabled to count at this moment, interrupt will be generated immediately and value of T1H and T1L will be loaded since it counts to FFFFH. So the T1H and T1L value should be set before enabling Timer1. August 15, 2003 Page 19 of 31 V1.2
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The contents of T1H and T1L almost loaded into Timer1 immediately when Timer1 is turned on after reset.
T1H
T1L
Auto reload when Timer1 underflow
"Timer1 Counter" decreases 1 No
Count TO 0xFFFFh
Start Timer1 Interrupt Request.
Yes
T1_INT
The Timer1 related control registers are list as below: Register Address Field Bit Position Mode IER T1L T1H OP1 0x02 0x03 0x04 0x09 TC1_IER T1L[7:0] T1H[7:0] TC1E 2 7~0 7~0 2
Description 0: TC1 interrupt is disabled. (default) R/W 1: TC1 interrupt is enabled. W Low byte of TC1 pre-load value W High byte of TC1 pre-load value 0: TC1 is disabled. (default) R/W 1: TC1 is enabled.
12. Timer2
Timer2 is similar in structure to Timer1 except that clock source of Timer2 comes from the system clock "Fsys"/1.5. The system clock "Fsys" varies depending on the operation modes of the MCU. The Timer2 consists of two 8-bit write-only preload registers T2H and T2L and 16-bit down counter. If Timer2 is enabled, counter will decrement by one with each incoming clock pulse. Timer2 interrupt will be generated when the counter underflows - counts down to FFFFH. And it will be automatically reloaded August 15, 2003 Page 20 of 31 V1.2
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with the value of T2H and T2L.
HE84760
HE80000 SERIES
Please note that the interrupt signal is generated when counter counts from 0000H to FFFFH. If the value of counter is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when system resets. Once it is enabled to count at this time, the interrupt will be generated immediately and value of T2H and T2L will be loaded since the counter counts to FFFFH. So the T2H and T2L value should be set before enabling Timer2.
The contents of T2H and T2L almost loaded into Timer2 immediately when Timer2 is turned on after reset.
T2H
T2L
Auto reload when Timer2 underflow
"Timer2 Counter" decreases 1 No
Count TO 0xFFFFh
Yes Start Timer2 Interrupt Request. T2_INT
The Timer2 related control registers are list as below: Register Address Field Bit position Mode IER T2L T2H OP1 0x02 0x05 0x06 0x09 TC2_IER T2L[7:0] T2H[7:0] TC2E 1 7~0 7~0 3
Description 0: TC2 interrupt is disabled. (default) R/W 1: TC2 interrupt is enabled. W Low byte of TC2 pre-load value W High byte of TC2 pre-load value 0: TC2 is disabled. (default) R/W 1: TC2 is enabled.
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HE80000 SERIES
13. Time Base Interrupt
The TB timer is used to generate time-out interrupt at fixed period. The time-out frequency of TB is determined by dividing slow clock with a factor selected in OP2[3..0]. TBE (Time Base Enable) bit controls enable or disable of the circuit. OP2 Field Mode Reset Bit 7 IDLE R/W 0 Bit 6 PNWK R Bit 5 TCWK R Bit 4 TBE R/W 0 Bit 3 W Bit 2 Bit 1 TBS[3..0] W W Bit 0 W -
TBE 0 1
Function Disable Time Base Enable Time Base
For example, if the slow clock is 32768 Hz, then the interrupt frequency is as shown in following table. TBS[3..0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Interrupt Frequency 16.384 KHz 8.192 KHz 4.096 KHz 2.048 KHz 1.024 KHz 512 Hz 256 Hz 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz 0.5 Hz
14. Watch Dog Timer
Watch Dog Timer (WDT) is designed to reset system automatically prevent system dead lock caused by abnormal hardware activities or program execution. WDT needs to be enabled in Mask Option. MO_WDTE Function 0 WDT disable 1 WDT enable To use WDT function, "CLRWDT" instruction needs to be executed in every possible program path when the program runs normally in order to clears the WDT counter before it overflows, so that the August 15, 2003 Page 22 of 31 V1.2
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HE84760
HE80000 SERIES
program can operate normally. When abnormal conditions happen to cause the MCU to divert from normal path, the WDT counter will not be cleared and reset signal will be generated. WDT is the enabling signal generated by calculating 32768-clock overflow. Reset Register content is same as TC1 (Timer1 clock), which uses the same clock count source. WDT function can be generated in Normal, Slow and Idle Mode. However, WDT will not function during Sleep Mode (as the TC1 clock has stopped.)
15. Digital-to-Analog Converter
The Digital-to-Analog converter (DAC) converts 7-bit unsigned speech data written to PWMC data register to proportional current. PWMC register DA & PWM Data Control Bit 7 0 1 Bit 6 Bit 4 Bit 3 Bit 2 DA and PWM output value PWM O/P driver Bit 5 Bit 1 Bit 0 PWME
There are two output paths for the DAC. Either VO or DAO can be selected as output port of DAC by VOC register when it is enabled. The VO output is primarily intended for speech generation, although it is not necessary so, while the DAO output path can be used in conjunction with built-in OP comparator to function as an Analog-to-Digital Converter as required in applications such as speech recording, speech recognition or sensor interfaces.
OPO OP + 1 PWMC[DATA] DAC 0 OPIP OPIN DAO VO R VOC[DAC] VOC[OP]
The DAC is enabled by DAC bit of VOC register. Please note that the DAC bit of VOC register will be automatically cleared when the system enter Idle or Sleep mode. So it needs to be set again when returning to Normal mode. VOC register Field Reset Bit 7 Bit 1 Bit 6 Name DAC Bit 5 Bit 4 Bit 3 Bit 2 PWM 0 Bit 1 DAC 0 Bit 0 OP 0
Value Function description 1 DA Enable 0 DA Disable
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The output current of the DAC is programmable by mask option MO_DACISEL: MO_DACISEL[1:0] DAC Output Current 00 0.375 mA 01 0.75 mA 10 1.5 mA 11 3 mA
HE84760
HE80000 SERIES
16. Pulse-Width Modulation
The pulse-width modulator (PWM) converts 7-bit unsigned speech data written to PWMC data register to proportional duty cycle of PWM output. PWM module shares the PWMC data register with Digit-to-Analog Converter. So PWM and DA output can exist at the same time. When PWM circuit is enabled, it generates signal with duty ratio in proportion to the DA value.
DA = 0x20
DA = 0x80
DA = 0xE0
1 subframe
The PWM bit of VOC register controls register to enable the circuit and output driver. When PWM bit of VOC is `0', PWME bit and output drivers settings are both cleared. To use PWM for voice output, PWM bit has to be set to `1' first, then set PWME bit and enable output driver by setting the driver number. If PWM bit is disabled and enabled again, the setting for driver and PWME bit will be clear. The Fast Clock is gated through PWME bit of PWMC command register to provide the clock source of PWM circuit when it is enabled. As PWM needs higher frequency to operate, it cannot generate correct PWM signal in Slow clock only mode. When the program enters into Sleep mode or Idle mode, it will automatically turn off all voice outputs by clearing VOC[2:1] to "00". To activate voice output again when returning to Normal Mode, the VOC register needs to be set again. The PWM output volume can be adjusted by command register PWMC[6:4]. The bit 6 and 5 control 2 time driver, while bit 4 controls 1 time driver, thus it has 5 levels of driver output. By turning on/off the internal drivers, the sound level of PWM output can be turned up and down. Please note that this adjustment apply only to PWM, but not DA output.
August 15, 2003
Page 24 of 31
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HE84760
HE80000 SERIES
PWM Output Driver Selection PWMC[6..4] 000 001 010 011 100 101 110 111 Number of Driver off 1 2 3 2 3 4 5
17. Dual-Tone Multiple Frequency Generator
The Dual-Tone Multiple Frequency (DTMF) generator is used to generate the Tone Dialing signal used in Telecommunication applications. In fact, it can be used to generate any two channel sinusoidal wave signal with frequencies ranging from 1 ~ 4095 Hz with 1 Hz resolution. The DTMF generator derives its clock from 32768 Hz. The DTMF generator is controlled through DTMFC (DTMF Control) Register. DTMFC can only be written, and it can not be read. The DTMFC register actually maps to Row Register, Column Register and Command Register. So when writing to DTMFC, the actual register being written is determined by Bit 7 and 6. DTMFC BIT7 ROW HIGH 0 ROW LOW 0 COL HIGH 0 COL LOW 0 COMMAND 1 BIT6 0 0 1 1 1 BIT5 M11 M5 M11 M5 HOOK BIT4 M10 M4 M10 M4 KT BIT3 M9 M3 M9 M3 CH1 BIT2 M8 M2 M8 M2 CH0 BIT1 M7 M1 M7 M1 DTMF BIT0 M6 M0 M6 M0 HB(1)/LB(0)
Bit 5 of command register (HOOK bit) is the main switch of DTMF Generator block. is `1', the entire block will be turned off and all internal registers will be not reset. `0', the block will be turned on.
When HOOK Bit When HOOK Bit is
The Row and Column registers determine the frequencies of two channels sine wave generator. As they are 12-bit register, they need to be divided into high parts and low part when writing. The procedure of changing the Row and Column frequency is by selecting High or Low byte to be written in the command register, write to the target register, then toggle the HB/LB bit, and then write to the second part of the register. When both frequencies are set, the DTMF tone can be sent to DTMFO output by turning on bit 1 (DTMF bit) of command register. When DTMF bit is `1', DTMF signal can be output, and the output is disabled when DTMF bit is `0'. August 15, 2003 Page 25 of 31 V1.2
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HE80000 SERIES
In addition to dual tone generation, the DTMF generation can be used to generate single channel tone determined by either ROW frequency or COL frequency or switching between the two frequencies with continuous phase. This feature is useful for generating phase coherent FSK (Frequency Shift Keying) tone as often used in Telecommunication. The frequency range is further expanded to 4095 Hz to cover the more range. For example, the Caller Alerting Tone requires 2130 and 2750 Hz tones to be generated which is beyond the range of the original design. Bit3 0 0 1 1 Bit2 Channel Select 0 Row + Column 1 Row frequency 0 Column frequency. 1 x
In addition to DTMF generation function, this function block also provides others features which are useful for the phone application. For example, Bit 4 (KT bit) of command register controls the generation of 1024 Hz square wave to provide the audio feedback to the user in response to key presses. When KT bit is `1', square wave generation is enabled, and when KT bit `0', the square wave is disabled. The DTMF and Keytone outputs are not dedicated output pins, but are multiplexed with I/O MO_KEYTONE. Mask Option MO_TONE MO_KEYTONE Value 0 1 0 1 Function Normal I/O pin (PRT10[0]) TONEO output through prt10[0] Normal I/O pin (PRT10[1]) KEYTONE output through prt10[1] PRT10[0] and PRT10[1]. The functions of these two pins are determined by mask options MO_TONE and
August 15, 2003
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HE80000 SERIES
18. Absolute Maximum Rating
Item Supply Voltage LCD Operating Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Sym. Rating Condition VDD -0.5V ~ 4.0V VLVL5 < 8.5 V VIN -0.5V ~ VDD+0.5V VO -0.5V ~ VDD+0.5V TOP 0C ~ 70C TST -50C ~ 100C
19. Recommended Operating Conditions
Item Supply Voltage Input Voltage Operating Frequency Operating Temperature Storage Temperature Sym. Rating VDD 2.4V ~ 3.6V VIH 0.9 VDD ~ VDD VIL 0.0V ~ 0.1VDD 8 MHz FMAX 6 MHz TOP 0 C ~ 70C TST -50C ~ 100C Condition
VDD =3.0V VDD =2.4V
August 15, 2003
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HE80000 SERIES
20. AC/DC Characteristics
Testing Condition : TEMP=25, VDD=3V10%
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Power consumption Normal mode current Slow mode Current Idle mode Current Sleep mode Current Additional Current if LCD ON I/O specification Input High Voltage Input Low Voltage Input Hysteresis Width Output Source Current Output Sink Current Input Low Current Input Low Current PWM and DAC PWM Output Current DAC Output Current Data Retention Data Retention Voltage IPWM IoVO VDR 10 6 4 2.5 1.2 14 8 5 3 mA mA mA mA Volts IFAST ISLOW IIDLE ISLEEP ILCD VIH VIL VHYS IOH IOL1 IIL1 IIL2 50 1.0 20 100 1/3 0.8 0.2 150 1 15 10 1.5 30 20 1 220 mA A A A A VDD VDD VDD A mA A A 1/7 bias, no load on SEG and COM pins Input Pins Input Pins I/O, RSTP_N Threshold = 2/3*VDD (Input from low to high), Threshold = 1/3*VDD (Input from high to low) Output drive high*1, VOL=2.0V Output drive low, VOL=0.4V RSTP_N, VIL = GND, Pull high Internally I/O, VIL=GND, if pull high Internally by user PWM *2 With 32 Loading With 64 Loading With 100 Loading VO, DAO@ VDD=3V,VO=0~2V, Data = 7F 2M external R/C fast clock 32768 Hz slow clock with LCD disabled 32768 Hz slow clock with LCD disabled
Notes:
1. 2. The "Output Source Current" specification is applicable only to the Push-Pull I/O type. This Specification indicates only one PWM driving capability, and there are totally five built-in drivers, user can multiply the actual number of driver to get the total amount of current. (IPWM * N; N=0, 1, 2, 3, 4, 5)
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HE80000 SERIES
21. Application Circuit
47K 47K
C7 VDD BUZZER 0.1uF PRTD0 PRTD1 PRTD2 PRTD3 PRTD4 PRTD5 PRTD6 PRTD7 PWM 47K
PWM
VDD 3.0V +
103 102 101 100 99 98 97 96 95 94
VDD PWM GND_PWM PRTD0 PRTD1 PRTD2 PRTD3 PRTD4 PRTD5 PRTD6 PRTD7 47K R PRT100 PRT101 PRT102 PRT103 TRIM0 TGND1 TRIM1 TRIM2 TGND2 TRIM3 VDD SXI SXO TSTP_P FXI FXO RSTP_N OPO OPIP OPIN VO GND LDL LFR LCAP2A LCAP3B LCAP2B LCAP1B LCAP1A LVL2 LVL1 LCDVX LCAP3A LCAP4A LCAP4B LCDVTB LVL3 LVL4 LVL5 LCDGS COM0 COM1 COM2 C0M3 C0M4 C0M5 C0M6 C0M7 C0M8 C0M9 C0M10 C0M11 C0M12 C0M13 C0M14 C0M15 C0M16 C0M17 C0M18 C0M19 C0M20 C0M21 C0M22 C0M23 C0M24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 PRT170 PRT171 PRT172 PRT173 PRT174 PRT175 PRT176 PRT177 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 PRT100 PRT101 PRT102 PRT103 33p 32768Hz 33p 47K 0.1uF
47uF PRTC7 0.1uF PRTC6 PRTC5 PRTC4 VDD CMSG32 CMSG33 CMSG34 CMSG35 CMSG36 CMSG37 CMSG38 CMSG39 CMSG40 CMSG41 CMSG42 CMSG43 CMSG44 CMSG45 CMSG46 CMSG47 CMSG48 CMSG49 CMSG50 CMSG51 CMSG52 CMSG53 CMSG54 CMSG55 CMSG56 CMSG57 CMSG58 CMSG59 CMSG60 CMSG61 CMSG62 CMSG63 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG49 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SGKY 43 SGKY 42 SGKY 41 SGKY 40 SGKY 39 SGKY 38 SGKY 37 SGKY 36 SGKY 35 SGKY 34 SGKY 33 SGKY 32 SGKY 31 SGKY 30 SGKY 29 SGKY 28 SGKY 27 SGKY 26 SGKY 25 SGKY 24 PRT147 PRT146 PRT145 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 PRTC7 PRTC6 PRTC5 PRTC4 VDD_RAM CMSG32 CMSG33 CMSG34 CMSG35 CMSG36 CMSG37 CMSG38 CMSG39 CMSG40 CMSG41 CMSG42 CMSG43 CMSG44 CMSG45 CMSG46 CMSG47 CMSG48 CMSG49 CMSG50 CMSG51 CMSG52 CMSG53 CMSG54 CMSG55 CMSG56 CMSG57 CMSG58 CMSG59 CMSG60 CMSG61 CMSG62 CMSG63 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SGKY 43 SGKY 42 SGKY 41 SGKY 40 SGKY 39 SGKY 38 SGKY 37 SGKY 36 SGKY 35 SGKY 34 SGKY 33 SGKY 32 SGKY 31 SGKY 30 SGKY 29 SGKY 28 SGKY 27 SGKY 26 SGKY 25 SGKY 24 PRT147 PRT146 PRT145
.... 47K SXI SXO TSTP FXI FXO RSTP OPO OPIP OPIN VO LDL LFR LCAP2A LCAP3B LCAP2B LCAP1B LCAP1A LVL2 LVL1 LCDVX LCAP3A LCAP4A LCAP4B LCDVTB LVL3 LVL4 LVL5 LCDGS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 PRT170 PRT171 PRT172 PRT173 PRT174 PRT175 PRT176 PRT177 1uF 1uF SGKY24 SGKY25 SGKY26 SGKY27 : SGKY41 SGKY42 SGKY43
VDD
1
2
47K
PRTC5
PRTC4
PRTC6 SCNI2
0 22p 4 MHz
SCNO17 SCNO18 SCNO19
SCNO0 SCNO1 SCNO2 SCNO3
SCNI0
SCNI1
22p
1uF 1uF
HE84760
1uF 1uF 4.7uF
This application assumes 48 COMX80 SEG configuration, and 80 SEG Extender KDS80.
SEG141 SEG140 SEG139 SEG138 SEG137 SEG136 SEG135 SEG134 SEG133 SEG132 SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 SEG125 SEG124 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99
59 60 61 62 63 64 65 66 67 68 69 70 72 73 71 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101
SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19
SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69
4.7uF 300K
58 57 56 55 54 53 52 51
4.7uF
SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149
SCNI3
PRTC7
KDS80
SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 VDD RES_N RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 GND STBN D_CN R_WN REN LDL LFR LVL2 LVL3 LVL5 LVP SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 RES RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 STBN DCN RWN REN LDL LFR LVL2 LVL3 LVL5 LVP SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 VDD
PRT144 PRT143 PRT142 PRT141 PRT140 PRT157 PRT156 PRT155 PRT154 PRT153 PRT152 PRT151 PRT150
1 2 3 4 5 6 7 8 9 10 11 12 13
August 15, 2003
PRT144 PRT143 PRT142 PRT141 PRT140 PRT157 PRT156 PRT155 PRT154 PRT153 PRT152 PRT151 PRT150
Page 29 of 31
SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91
1 2 3 4 5 6 7 8
SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11
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22. Important Note
1. Please note that ICE is different from IC. ICE is the super set of HE80000 series IC, but each IC is a subset of ICE. Never use any hardware resource that real IC doesn't have, especially RAM and register. KBIDS and compiler cannot prevent user to use some hardware resource that didn't exist. Please use ICE5.x (Type-III LCD Driver) to emulate the equivalent effect of Type-IV LCD driver. The same bias and LV5 will get almost the same result of display effect. Adjust your bias and LVL5 on ICE 5.x and make sure the display of LCD is OK. Then the display effect of 84760 (Type-IV LCD driver) will be the same at the same bias and LV5. When accessing any address large than 64KB, users must update TPP first, TPH then TPL. Only by this order, the pre-charge circuit of ROM will work correctly. 5us waiting is necessary before LDV instruction is executed since Data ROM is a low speed ROM. Users can not emulate this accessing process on ICE. So 5us delay should be added by firmware. LCD driving circuit must be turned off before IC goes into sleep mode. Please bond the TSTP_P, RSTP_N and PRTD[7:0] with test points on PCB, which can be soldered and probed, and connect TSTP_P pin with zero ohm resistor to GND (or copper wire which can be cut easily on PCB) for good ESD protection. So that IC testing can be done on PCB, if necessary by removing the 0-ohm resistor and driving TSTP_P pin to high. LV5 must be lower than 8.5 Volt. Otherwise IC may breakdown. The voltage adjustment mechanism shall be reserved for LV2 voltage fine-tunes; since it's possible there is some variation in LV2 voltage due to IC manufacture process variation. User can use variable-resistor to adjust the LV2 voltage or use some tools to detect the LV2 and then select a proper resistor. Please refer to application note AN025 for the detailed description. Users must call the library "swap_page" in the file swappage.asm of application note AN029. The real IC register is different from ICE4.x or ICE5.x. This subroutine makes sure that users can run on both real IC and ICE for page swapping. The program of swappage.asm as following: .area swapping_variable(data) _mapreg1:: .ds 1 ;store page register(R1Bh) mapreg2:: .ds 1 ;store page register(R1Ch) .area swappingpage(code,pag0) ;====================================================== ;swap page function ;====================================================== swappage:: lda #10h sta mapreg1 lda #00h ; P1EO[2] <--0 to enable Port R1Fh sta riceco ; RICECO is write only August 15, 2003 Page 30 of 31 V1.2
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2.
3.
4. 5.
6. 7.
8.
King Billion Electronics Co., Ltd
lda mapreg2 sta riced lda _mapreg2 anda #0fh ora #20h ;Mapping mapreg2 low nibble to Logical segment2 sta r1Ch sta rps1 lda _mapreg2 rorc rorc rorc rorc anda #0fh ;Mapping _mapreg2 high nibble to Logical segment3 ora #30h ; sta r_ps1 sta r1Ch ret
HE84760
HE80000 SERIES
;
23. Updated Record
Version Date Section July26,2002 D,G,H 1.1 Feb 13, 2003 1.2 Original Content New Content Add TGND1 and TGND2 pins. Added function block descriptions
August 15, 2003
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V1.2
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